DK-DEV-5SGXEA7N【PDF 275/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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10-4

Supported JTAG Instruction

SV51012

2014.01.10

JTAG Instruction

EXTEST

BYPASS

USERCODE

IDCODE

Altera Corporation

Instruction Code

00 0000 1111

11 1111 1111

00 0000 0111

00 0000 0110

Description

? Allows you to test the external

circuit and board-level intercon-

nects by forcing a test pattern at the

output pins, and capturing the test

results at the input pins. Forcing

known logic high and low levels on

output pins allows you to detect

opens and shorts at the pins of any

device in the scan chain.

? The high-impedance state of EXTEST

is overridden by bus hold and weak

pull-up resistor features.

Places the 1-bit bypass register between

the TDI and TDO pins. During normal

device operation, the 1-bit bypass

register allows the BST data to pass

synchronously through the selected

devices to adjacent devices.

? Examines the user electronic

signature (UES) within the devices

along a JTAG chain.

? Selects the 32-bit USERCODE register

and places it between the TDI and

TDO pins to allow serial shifting of

USERCODE out of TDO .

? The UES value is set to default value

before configuration and is only

user-defined after the device is

configured.

? Identifies the devices in a JTAG

chain. If you select IDCODE , the

device identification register is

loaded with the 32-bit

vendor-defined identification code.

? Selects the IDCODE register and

places it between the TDI and TDO

pins to allow serial shifting of

IDCODE out of TDO .

? IDCODE is the default instruction at

power up and in the TAP RESET

state. Without loading any instruc-

tions, you can go to the SHIFT_DR

state and shift out the JTAG device

ID.

JTAG Boundary-Scan Testing in Stratix V Devices

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